The present invention relates to a method of fabricating a semiconductor integrated circuit substrate including an insulated-gate field effect transistor element and to a novel semiconductor integrated circuit substrate, and more particularly, to a method of shortening the Turn Around Time (hereafter referred to as TAT) involved in process development by monitoring the electrostatic destruction withstanding value of the substrate.
FIG. 19 shows a typical top plan view of a general terminal configuration of a mold-packaged semiconductor integrated circuit (hereafter referred to as IC). For the IC, the terminals used for connection with an external circuit are roughly divided into the following four types: Vcc terminal 171, ground terminal 172, input terminal 173, and output terminal 174. The semiconductor integrated circuit arrangement comprises these terminals for interconnection to external circuits and an internal circuit for performing a predetermined logical processing and the like. In most applications, an insulated-gate field effect type (hereafter referred to as MOS type) transistor, diode, resistor, and capacitor and the like are integrated as basic components of an integrated circuit device.
For facilitating understanding of the present invention, a MOS transistor associated with a terminal section is particularly called a peripheral transistor and that associated with an internal circuit is called an internal transistor. One of the more important reliability factors for ICs is the electrostatic destruction withstanding value (hereafter referred to as ESD withstanding value). This is a value specified by EIAJ, and requires that ICs must withstand against an ESD stress of a machine model of approx. 200 pF, 250 V.
FIG. 20 shows a typical circuit schematic diagram for an ESD stress test. In this case, a state is shown in which +250 V of the GND standard is applied. After the voltage is applied, the leakage current of each of the terminals and that between the power supply terminals are measured. FIG. 21A is a graph showing the relationship between ESD stress and leakage current of each of the terminals after stress is applied. A current originally of a .mu.A order increases in accordance with applied stress voltage. The current suddenly increases at the point where stress voltage exceeds a certain value, a point, for example, where the leakage current exceeds 1 .mu.A is decided as the ESD withstanding value.
FIG. 22 shows a typical block diagram of a general input-terminal protective circuit. The N-channel MOS transistor 201 is the one which performs a function for protection against an ESD stress as a so-called off-transistor. Details of such a device are described in Japanese Patent Application No. 048876-1992. FIG. 23 shows a typical block diagram of a general N-channel open drain output terminal.
In recent years, the remarkable decrease of the ESD withstanding value of N-channel MOS transistors used for the open drain output has become a problem because ICs have been made in extraordinary high density. The structural dependency of ESD withstanding voltage in transistors and improvement measures therefor are also shown in Japanese Patent Application No. 048876-1992. The structure described therein includes a structure to be settled by such as thickness of a gate insulated film and concentration of an impurity area in the fabrication step and that to be settled by planar dimensions and arrangement, which is design rule like. In the present invention, however, the both structures are generally called a process menu or process.
FIG. 24 shows another typical block diagram of a protective circuit for an N-channel open drain output terminal. FIG. 25 shows a typical block diagram of a protective circuit for a CMOS output terminal. FIG. 26 shows a block diagram of a protective circuit for an input/output terminal. Various input/output terminals have been explained above, however, it is understood that ICs are generally provided with an N-channel MOS transistor in recent years. Description is continued hereinafter in consideration of this fact.
FIG. 17 is a flow chart showing the design and development of a general IC. Description herein is made with reference to the flow chart. First, a process to be used (the process here includes design rule) is selected according to the project of the new IC taking into consideration whether various processes can produce an IC having the necessary performances and whether it can be fabricated in a desired chip size using such processes. Then, a circuit is designed according to the above consideration. Then, a prototype is fabricated in the trial production step. Then, the performances and characteristics are measured and evaluated. In this case, an ESD test is performed simultaneously with an endurance test or the like. Then, unless the prototype meets the specification, it is rejected and process selection and circuit design are tried again on a trial and error basis. Normally, six months to one year are necessary for one cycle even if no trouble occurs. If the prototype is rejected in the ESD test, an additional six more are necessary in the case where planning is carried out from the circuit design step. The fact that the ESD withstanding value is not accurate until the final stage of product development is a serious problem, in that it has a critical influence on the TAT which is already too long, even under normal conditions.
FIG. 18 shows a flow chart of a general process development. Although process development refinement is not limited to the case of increasing circuit density and speed, such a development cycle is shown in FIG. 18. First, a design rule is temporarily set. Then, a fabrication step is set, a photomask for only a test pattern dedicated to development (frequently called TEG) is designed, and a prototype is fabricated in the fabrication step. For a finished semiconductor wafer, various electrical characteristics are carefully measured, evaluated, and judged. Unless there is any resulting problem, the design rule and fabrication step are approved and released to the circuit design group. In general, satisfactory results are not obtained in the fabrication of a prototype in the fabrication step and therefore modification of the design rule or modification of the fabrication step is required. It is normally repeated three or four times depending on the degree of circuit complexity. The TAT for development of a new process generally requires at least 1 to 3 years. Therefore, when a product is developed using a new development process but fails the ESD test in the final step, this results in disastrous consequences because the process development must be started over from the beginning stage, and the cause of the problem must be determined. In this case, the TAT may undesirably require several years.
Even in an already-released IC, there may be a product which frequently causes a problem in a market or field because there was originally no margin in the ESD withstanding value when the product was designed. Also, there may be a product which accidentally passes the ESD test in qualification for a new product and whose ESD withstanding value is proved to be insufficient due to the subsequent processing in the fabrication step after mass production of the product starts. There may be a problem in the process menu or in the circuit design and the like of the product. In any case, design and development must be performed a new because it is impossible to sort the products through the ESD test after they are mass-produced and packaged. During the period of redesign, shipping of such defective products is generally stopped. Therefore, this has caused a large, industry-wide problem.